The combination of an increased demand for consumer electronics and the continued growth in semiconductor packing density is driving towards the integration of more and more system functionality onto a single integrated circuit (IC). The result, among other things, is an increased need for the integration of analog and mixed-mode components (eg. analog-digital, RF-analog-digital, and mechanical-analog-digital) on the same chip as the digital components. Designing such mixed-signal systems-on-chip (SOCs) is distinctively challenging since it entails managing system level abstractions while simultaneously dealing with physical effects at the transistor and parasitic levels. In the same manner, testing next-generation SOCs represents a real challenge, especially since cost and time-to-market are usually key requirements. Such mixed-signal ICs contain complex signal paths and functional specifications, and post-design ad hoc test program development will no longer be viable since it can significantly slow down device characterization and debugging, and it can tie up automatic test equipment (ATE) resources (in the production phase) and greatly increase the time-to-market.
The difficulty is accentuated by another aspect of system-level integration, namely, the integration of third-party cores. In order to cope with design complexity, final system manufacturers are forced to rely on pre-designed blocks, or “cores,” and to integrate these cores as part of the bigger, more complex systems. These cores are obtained from virtual library (software) descriptions of the final IC block. In the digital domain, test access mechanisms (e.g. through scan) and design-for-test (DfT) techniques are already in place for the most part, and test information (digital bits) can be transported without loss throughout the SOC and across the chip boundary to the outside world. Thus, it seems possible to derive a systematic procedure by which the final system integrator can access the embedded digital virtual cores. The problem in the analog domain is the fact that it is a Jot harder to “scan” signals over long distances in a chip and across the chip boundary to the outside world. Rapid signal degradation due to digital noise coupling or analog buffer distortion characteristics is very likely to occur.
In the present state of the art, analog and mixed-signal parts are tested externally for the most part. Even as core-based design grows in popularity, the most critical high-frequency analog cores are still allocated dedicated and handcrafted I/O access so that they can be tested to specifications using external instruments. This being said, recent attempts at integrating some test functionality have been made, although they remain to be ad-hoc and customized in nature. For example, with reference to FIG. 1, an on-chip ramp generator for the code-density testing of A/D converters known in the art is illustrated. However, this technique is very specific to a certain class of A/D converters. As well, a sine-wave generator using an oversampling delta-sigma oscillator has recently been proposed (FIG. 2a). To avoid the design complexity associated with such an oscillator, a circular memory based approach that approximates the output of a delta-sigma oscillator has been reported (FIG. 2b). This proposed design has the advantage of flexibility and the potential for a higher speed of operation. When both an A/D and a D/A converter are present, prior art assumes the A/D can be tested somehow (e.g. using the circular memory approach), and then the A/D is used to test the D/A (FIG. 3). Beyond A/D and D/A converters, other techniques use an analog test bus to matrix signals around the chip to boundary elements containing switches, buffers, and/or comparators.
As can be seen, the above approaches are limited customized solutions or are generally cumbersome to implement in a virtual core-based design environment. There is a need for a general integrated excitation/extraction system for analog test and measurement.